Cadence PCIe Solutions: Configurable, Compliant, and Low Power
Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since then, our PCIe offerings have evolved to include the lowest power PHY solutions available, FPGA platforms for prototyping, software drivers, and the industry’s leading verification IP.
To read the full article, click here
Related Semiconductor IP
- Controller for PCIe
- 10Gbps Multi-Link and Multi-Protocol PHY IP
- 10Gbps Multi-Protocol PHY IP
- Controller for CXL
- Simulation VIP for CXL
Related Blogs
- PCIe Low-Power Validation Challenges and Potential Solutions (PIPE/L1 Substates)
- How to Maximize PCIe 6.0's Advantages with End-to-End PCIe Design Solutions
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space