Cadence IP Report Card 2013
March 18, 2013
The challenges of developing IP blocks, integrating them correctly, and hitting the power, performance, area, and time to market requirements of a mobile SoC is a growing problem. At 20nm and 14nm the probability of a chip re-spin due to an error is approaching 50% and we all know how disastrous a re-spin can be, those are not good odds even in Las Vegas.
Cadence talked a bit about IP during the CDNLive keynotes last week and even more so during a press lunch. Paul McLellan and I also spent time with Cadence IP Commander in Chief Martin Lund. Given the recent IP acquisitions it is clear that Cadence is serious about scaling their business so I have to give them an A+ on IP strategy thus far.
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Related Semiconductor IP
- Adaptive Voltage Scaling (AVS) Bus Target IP
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- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
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- Dream Chip, Cadence Unveil Automotive SoC with Tensilica IP at embedded world '25
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
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