Cadence IP Is Great for Automotive
September 13, 2017
If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort.
We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs.
To read the full article, click here
Related Blogs
- Dream Chip, Cadence Unveil Automotive SoC with Tensilica IP at embedded world '25
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- How Physical AI Is Redefining the Automotive Industry
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions