Anti-Fuse Memory With Gusto
Magnetic RAM, Cross-Bar, Trapped Charge, Ferroelectric are all non-volatile memory technologies which I've heard of but, until yesterday, I hadn't heard of an antifuse-based NV memory.
Kilopass of Santa Clara has been beavering away for nine years using anti-fuse to make OTP memories which it sells as hard macros for embedding in ASIC/SOCs, eliminating the need for external serial flash and EEPROMs in mobile devices.
To read the full article, click here
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Blogs
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
- Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
- Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?
- Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?