A Great Match: SoC Verification & Hardware Emulation
Design and verification project groups have a new tool in the arsenal that will enable better hardware emulation results, greater efficiency, and increased productivity.
More than once, I have heard design and verification project groups complain about the lack of a unified and consistent SoC (system-on-chip) verification process. Almost all of them were juggling the wide range of verification technologies in their environments, including simulation, simulation acceleration, emulation, prototyping, and silicon validation -- and they certainly were not juggling efficiently. This has gone on for years and is only getting more complicated.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Blogs
- Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?
- Crypto mining SoC unearths a need for custom IP
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Why Vision LLMs Force A Rethink Of Edge AI Hardware
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution