A Great Match: SoC Verification & Hardware Emulation
Design and verification project groups have a new tool in the arsenal that will enable better hardware emulation results, greater efficiency, and increased productivity.
More than once, I have heard design and verification project groups complain about the lack of a unified and consistent SoC (system-on-chip) verification process. Almost all of them were juggling the wide range of verification technologies in their environments, including simulation, simulation acceleration, emulation, prototyping, and silicon validation -- and they certainly were not juggling efficiently. This has gone on for years and is only getting more complicated.
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