Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
TRC6002CSA is a Dual Serial ATA (SATA) Host PHY core for interfacing serial data between Storage Device and external 2-port PHY.
- Single-Protocol PHY
Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
TRC6002CSA is a Dual Serial ATA (SATA) Host PHY core for interfacing serial data between Storage Device and external 2-port PHY.
Serial ATA I/II/III Host Controller IP Core Compliance Certified by UNH Labs
The Serial ATA Host Controller IP Core provides an interface to highspeed serial link replacements for the parallel ATA attachmen…
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a range of host and device functions, UMC 0.13um HS/FSG Logic process.
The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
Serial ATA (SATA) PHY Transceiver IP
SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
SATA-IP core - File system management without CPU
SATA IP core compliant with the Serial ATA specification revision 3.0 and work on AMD UltraScale and 7-Series device.
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA S…
Dual SATA Host controller on Virtex 5 FXT FPGA
The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyc…
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA AR…
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA.
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA.
The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass …
IP
ZYNQ SATA 3 AHCI Host Controller with Linux Driver
The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a…
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA C…
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed gra…