Vendor: Logic Design Solutions Category: SATA Controller

Serial ATA Dual Host Controller

The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA.

Overview

The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5 IP is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable to GEN 2. The LDS SATA HOST DUAL XV5 IP is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of GEN1 speed selection and 75MHz in case of GEN 2 speed selection. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.

Key features

  • Physical Layer features
    • Detect OOB and COMWAKE
    • Detect the K28.5 comma character and provide a 16 bit parallel output
    • Power management mode handled by state machine (shared between Phy and Link layer)
    • Provides error indication to upper layers
    • 8b/10b encoding and decoding in Xilinx Virtex 5 GTP Macro
    • Fixed speed seclection
  • Link Layer features
    • Scrambling of tx data and descrambling of rx data
    • CRC 32 calculation and check from Xilinx Virtex 5 hard macro
    • Report transmission status and error to Transport Layer
    • Enable BIST loopback and pattern generation modes
    • Auto inserted hold primitive to avoid FIFO overflow and underflow
    • Partial and slumber power management modes
    • The interface between the link layer and the transport layer is 32-bit wide
  • Transport Layer features
    • 48-bits sector address
    • Programmed IO (PIO) and DMA modes
    • Support BIST FIS transmission and reception
    • Automatic error FIS retry capability
    • Implement Shadow Registers and SATA SuperSet registers
    • Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
    • DMA interface can be connected easily to memory space or FIFOs
    • Support DMA Abort primitive
    • 128-Word Ingress and Egress FIFO between Transport and Link Layer

Specifications

Identity

Part Number
LDS SATA HOST DUAL XV5
Vendor
Logic Design Solutions
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

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Frequently asked questions about SATA Controller IP

What is Serial ATA Dual Host Controller?

Serial ATA Dual Host Controller is a SATA Controller IP core from Logic Design Solutions listed on Semi IP Hub.

How should engineers evaluate this SATA Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SATA Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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