TaraCom announces GPON SerDes IP PHY in 90 nm process
TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC design.
Vendor:
TaraCom Integrated Products, Inc.
Category:
Single-Protocol PHY
Dual Serial ATA 1.5/3.0/6.0 Gbps Phy
TRC6002CSA is a Dual Serial ATA (SATA) Host PHY core for interfacing serial data between Storage Device and external 2-port PHY.
Overview
TRC6002CSA is a Dual Serial ATA (SATA) Host PHY core for interfacing serial data between Storage Device and external 2-port PHY. TRC6002CSA uses double data rate (DDR) transmission for send and receive side. The Device can operate as a Serial ATA Gen I at 1.5 Gbps, Gen 2 at 3.0 Gbps and Gen 3 at 6.0 Gbps. Spread Spectrum Clock (SSC) is used to minimize EMI and increase the quality of received signal. It can transmit and receive through a 40-inch cable. Each transmit section of the TRC6002CSA contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial converter with built in 8b/10b encoder, and differential high speed Interface output. Its receive section contains an input limiting amplifier with on-chip terminations, a clock/data recovery PLL, a Comma detector, a serial to parallel converter with built-in 8b/10b decoder. OOB circuitry complies with SATA Gen 1,Gen 2, and Gen 3 Standards, featuring COMRESET/COMINIT, and COMWAKE commands and detection. TRC6002CSA has a built-in Near and Far End Loopbacks. SLUMBER and PARTIAL Power Down feature minimize the power consumption of device. TRC6002CSA is fabricated with TSMC’s advanced 40 nm G CMOS logic process, and is portable to other processes.
Key features
- Serial ATA fully compliant to Gen 1,Gen 2 and Gen3 SATA Phy Standards.
- Transmit and receive data at 1.5Gbps, 3.0 Gbps and 6.0 Gbps.
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution
- Jitter Tolerance is better than Specifications.
- 8bit/ or 10bit parallel interface logic.
- 8b/10b encoder and decoder
- High speed serial drivers
- High speed serial input stage with on-chip terminations
- Comma Detect for character alignment
- Far and Near End serial loopback test modes.
- Multi pattern generator and PRBS error checker to support BIST
- Three programmable levels of pre-emphasis and equalization.
- Standard OOB sequencing with optional bypassing OOB capability.
- 1.0V/1.8V ±5% Supply for logic core and control I/O.
- Low power, 120 mW max per channel.
Specifications
Identity
Part Number
TRC6002CSA
Vendor
TaraCom Integrated Products, Inc.
Type
Silicon IP
Files
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Provider
Learn more about Single-Protocol PHY IP core
TaraCom Introduces SerDes/PHY IPs in 90 and 65-Nanometer
TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA,
Frequently asked questions about Single-Protocol PHY IP
What is Dual Serial ATA 1.5/3.0/6.0 Gbps Phy?
Dual Serial ATA 1.5/3.0/6.0 Gbps Phy is a Single-Protocol PHY IP core from TaraCom Integrated Products, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.