PCI Express Gen3 SERDES PHY on TSMC CLN40G
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 SERDES PHY on Samsung 7LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3 SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…
PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCIe Gen3 Class SSCG PLL on TSMC CLN16FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on TSMC CLN12FFC
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
PCIe Gen3 Class SSCG PLL on GLOBALFOUNDRIES 12LP
The PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI E…
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
Xilinx provides a PCI Express Gen3 integrated block for PCI Express® (PCIe) in the Virtex®-7 XT and HT family of FPGAs.
UltraScale Gen3 Integrated Block for PCI Express (PCIe)
Xilinx provides a PCI Express Gen3 Integrated block for PCI Express® (PCIe) in the UltraScale™ family of FPGAs.
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support…
AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC an…
PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The High Speed 16GHz PLL generates a low jitter frequency outputs.
UltraScale+ Device Integrated Block for PCI Express (PCIe)
The Xilinx® UltraScale+ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable seria…
Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementat…
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…