IP
- Single-Protocol PHY
IP
PCI Express Gen2 PHY IP, PCIe Gen-2, 4 Lanes, UMC 90nm SP process
4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process.
Virtex-5 FPGA, Gen1 PCI Express The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-la…
The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interfa…
The PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interfa…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…
PCIe Gen 6 controller IP
PCIe Verification IP provides an smart way to verify the PCIe bi-directional bus.
SRIOV Verification IP provides an smart way to verify the PCIE bi-directional bus.
PCI Express Synthesizable Transactor
PCIE Synthesizable Transactor provides a smart way to verify the PCIE component of a SOC or a ASIC in Emulator or FPGA platform.
PCIe Gen 5 - Validates high-speed designs, ensuring compliance and error-free performance
PCIe Gen 5 Verification IP offers a robust solution for validating designs based on the PCI Express 5.0 specification, delivering…
The AXI Bridge for PCIe IP core is the IP solution with a mix of multiple industry standard memory mapped AXI Interfaces.The AXI …
The USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF).
The SerDes PHY IP meets the requirements of broad range of market segments including network communication, PC interconnect, data…
Multi-Channel Flex DMA IP Core for PCI Express
The Multi-Channel DMA IP Core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.