DisplayPort Link Controller IP Listing

The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of vide…

• Single-Protocol PHY

Our 6th generation DisplayPort Receiver Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPort …

• Displayport

Our 6th generation DisplayPort Transmitter Link Controller core supports DisplayPort 2.1, DisplayPort 1.4a and embedded DisplayPo…

• Displayport
• In Production
• Immediate
• DisplayPort 1.4, eDP 1.4a, …

The DisplayPort Link Policy Maker (LPM) is a DisplayPort 1.4/2.0 compliant software stack that manages and controls the DisplayPo…

• Displayport

Synopsys has pre-integrated USB-C 3.1/DisplayPort 1.4 IP into a single subsystem solution to save customers more than two enginee…

• USB

The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devi…

• Displayport

The DisplayPort transmitter PHY version 1.4 can transmit data at rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• Single-Protocol PHY
• In Production
• Immediate

The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devic…

• TSMC
• 12nm
• FFC
• In Production

Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• TSMC
• 40nm
• LP
• In Production

Version 1.4 of the DisplayPort transmitter PHY is capable of transmitting data at rates of 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• UMC
• 40nm
• LP
• In Production

The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• UMC
• 28nm
• HPC
• In Production

The DisplayPort transmitter PHY version 1.4 supports data rates between 1.62Gbps (RBR) to 5.4Gbps (HBR2).

• TSMC
• 28nm
• HPC+
• In Production

The maximum capacity of the Display Port 1.4 Rx IP Channel is supported.

• Single-Protocol PHY
• In Production
• Immediate

Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…

• Single-Protocol PHY
• In Production
• Immediate
• DisplayPort version 1.4 rec…

The Display Port 1.4 Rx IP Channel's maximum capacity is supported.

• UMC
• 40nm
• LP
• In Production

This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth,…

• TSMC
• 40nm
• LP
• In Production

The capacity of the Display Port 1.4 Rx IP Channel is supported.

• UMC
• 28nm
• HPC
• In Production

Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…

• TSMC
• 28nm
• HPC+
• In Production

The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…

• Displayport

The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…

• Displayport