Highly scalable performance for classic and generative on-device and edge AI solutions
Scalable and Power-Efficient Neural Processing Units The Neo NPUs offer energy-efficient hardware-based AI engines that can be pa…
- Edge AI Accelerator
Highly scalable performance for classic and generative on-device and edge AI solutions
Scalable and Power-Efficient Neural Processing Units The Neo NPUs offer energy-efficient hardware-based AI engines that can be pa…
400G/800G High Speed Ethernet Controller PCS/FEC
Up to 800G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet…
10G to 400G High Speed Ethernet Controller MAC/PCS/FEC
Up to 400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet…
200G/400G High Speed Ethernet Controller MAC/PCS/FEC
200G/400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet …
1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
200G aggregate bandwidth channelized solution for up to four Ethernet channels Cadence High Speed Ethernet Controller IP supports…
10G to 400G High Speed Channelized Ethernet Controller MAC/PCS/FEC
400G aggregate bandwidth channelized solution for up to eight Ethernet channels Cadence High Speed Ethernet Controller IP support…
400G/800G High Speed Ethernet Controller MAC/PCS/FEC
800G/400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet …
Providing a Solution for HBM4 The Cadence High-Bandwidth Memory generation 4 (HBM4E) PHY is optimized for systems that require th…
DDR5 MRDIMM PHY and Controller
-edge IP for high-performance multi-channel memory systems The DDR5 12.8Gbps MRDIMM Gen2 PHY and controller memory IP system solu…
Tensilica DSP IP supports efficient AI/ML processing
The Cadence AI IP platform includes the extensible DSP platform from Cadence, which provides flexible instruction sets designed t…
Integrates MAC IP to a broad range of PHY and SerDes IP The Cadence Ethernet XAUI Physical Coding Sublayer (PCS) IP provides the …
Dual-Role Device Controller for USB 3.0
Mature solutions featuring xHCI Host, Device, and Dual-Role Certified for compliance with USB 3.0 Specification v1.0, and xHCI Sp…
Mature solutions featuring xHCI Host, Device, and Dual-Role Compliant with Universal Serial Bus 3.0 Specification, Revision 1.0 a…
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-lo…
Efficient scaling of AI accelerators is necessary for achieving breakthrough performance and throughput in modern compute environ…
The Gold Standard Memory Model is intended to be compatible with the anticipated JEDEC LPDDR6 standard for your IP, Subsystem, So…
Simulation VIP for Ethernet UEC
Best-in-class Ethernet Verification IP for your IP, SoC, and System-level Design Testing The Cadence Verification IP (VIP) for Et…
The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a bus functional model (BFM) with integrated automatic protoco…
Simulation VIP for AMBA CHI-C2C
Best-in-class Arm® AMBA® CHI-C2C Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a matur…
224G SerDes PHY and controller for UALink for AI systems
Efficient Scaling of AI Accelerators for Achieving High Performance and Throughput UALink, the standard for AI accelerator interc…