Vendor: Cadence Design Systems, Inc. Category: UALink

Simulation VIP for UALink

The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a bus functional model (BFM) with integrated automatic protoco…

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a complete bus functional model (BFM) with integrated automatic protocol checks for physical layer in addition to Media Independent Interface (MII). Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality. The VIP for UALink can be used as a standalone PHY verification with jump-start test suite – Integration Test Suite (ITS) provided. The VIP for UALink supports a wide range of verification platforms, all major simulators, and the industry-standard Universal Verification Methodology (UVM). The VIP core is written in native C++ language for excellent performance, with seamless integration with verification languages. Supported specification: UALink 200G Rev1.0 specification

Supported specification: UALink 200G Rev1.0 specification

The following table lists the key features offered in the Cadence VIP for UALink:

Feature Name

Description

Device Type
  • Accelerator Device, PHY DUT

Interface
  • Serial, Media Independent Interface (MII)

Link Rate
  • Supports all UALink Speeds:
    • 200G, 400G, 800G; Base Speed: 200GPL
    • 100G, 200G, 400G; Base Speed: 100GPL

Link Width
  • Configurable link width support x1, x2, x4

PMA Bus Width
  • Configurable PMA bus width: 1,2,4,10,16,20,32,40,48,64,66,80,96,120,128,160,240,320 Bits

Bifurcation
  • Supports multi-port configuration: 4 ports x1 lane, 2 ports x2 lanes, 1 port x4 lanes

Key features

  • Compliance to IEEE 802.3dj physical layer specification
  • Verifies Standalone PHY DUT with x1, x2, x4 native widths and 100G, 200G, 400G, 800G speed
  • 1-way, 2-way, 4-way interleaving supported
  • Comprehensive protocol checks with 130+ built-in checks/assertions
  • Serial and PMA bus widths listed at UALink level and MII between DL and PHY
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Static and dynamic setting for configuration variables available

Block Diagram

Simulation VIP for UALink block diagram

Benefits

  • Power-Efficient Design: Optimized for UALink
  • Low-Latency: For maximum design performance
  • Proven Solution: Full protocol stack implemented and verified in test chips
  • Long-Reach Capability: Robust 224G 47+dB LR performance with LR/MR/VSR support at reduced power

Specifications

Identity

Part Number
Simulation VIP for UALink
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about UALink IP core

UALink Under the Hood: Why Full-Stack Verification Wins

Verifying UALink means following a transaction the way the silicon does: down through four layers, out across one, two, or four SerDes lanes at the configured 100G or 200G serial rate, and back again, with its meaning and its bytes both intact. This blog takes that journey one layer at a time, and along the way examines a detail of the data link flit that is easy to overlook and important to get right.

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As an early contributor to the UALink ecosystem, Cadence delivers a production-ready solution built for real-world AI deployments. By combining high-performance connectivity IP with integrated security, Cadence enables customers to scale AI infrastructure with confidence.

Validating UPLI Protocol Across Topologies with Cadence UALink VIP

The UPLI (UALink Protocol Level Interface) is a logical signaling interface that facilitates communication between devices—specifically between originator devices (which initiate transactions) and completer devices (which respond to them). Each transaction comprises a request and a corresponding response, forming a complete communication cycle. Cadence UALink VIP supports various topologies to verify UPLI layer of DUT.

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

At the recent ECOC 2025 conference in Copenhagen, Cadence showcased its key role in enabling the future of AI infrastructure with live silicon demonstrations of several essential IP technologies for emerging 800G and 1.6T networks. Powered by Cadence's 224G SerDes IP, Cadence's Ultra Accelerator Link (UALink 1.0) scale-up and Ultra Ethernet scale-out networking solutions deliver the performance, flexibility, and interoperability needed for next-generation AI factories and hyperscale data centers.

AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP

In this second blog of our ongoing series, we examine how Cadence, in close partnership with TSMC, helps teams accelerate AI silicon design at advanced process nodes. For customers, this translates into reduced design risk, faster convergence to tapeout‑quality results, and greater confidence at the leading edge of AI and HPC design.

Frequently asked questions about UALink IP cores

What is Simulation VIP for UALink?

Simulation VIP for UALink is a UALink IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this UALink?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP