SAS-3 IP Listing

SAS Verification IP provides an smart way to verify the SAS bi-directional bus.

• Verification IP

The SAS Synthesizable Transactor verifies SAS interfaces of designs SAS Interface.

• SAS

The SAS Initiator IP core is fully compliant with Serial ATA SCSI 5.0 Specification.

• SAS

Avery SAS VIPs support verification of host and device and expansion targets.

• Verification IP

The Cadence® Verification IP (VIP) for SAS is part of Cadence’s broad storage interface verification IP (VIP) portfolio.

• Verification IP

The IntelliProp SAS Bridge with Sandbox (IPP-SS115A-BR) design provides SAS compliant connections to a SAS host and a SAS device.

• SAS

The IntelliProp IPC-SS105A-HI SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host desig…

• SAS

The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications.

• SAS
• Production
• Now
• SAS 12G

The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment…

• SAS
• Production
• Now
• SAS 12G

The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to …

• SAS

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS) capable…

• TSMC
• 16nm
• FFC

IP

• Optical Transport
• Silicon Proven

With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …

• Single-Protocol PHY

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.

• Single-Protocol PHY
• Serial ATA (SATA) I/II, Ser…

1-VIA’s ultra-high-speed and ultra-low-power PCIe Gen 3/4/5 SerDes technology is customizable to meet your requirements for a wid…

• Multi-Protocol PHY

Media Access Control Security (MACSec) is an IEEE standards-based protocol for securing communication among the trusted component…

• MACsec

Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…

• TSMC
• 40nm
• LP

PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps.

• TSMC
• 40nm
• G

Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.

• TSMC
• 3nm
• N3P
• Pre-Silicon

The MVCLK02 is a high-precision and programmable clock generator circuit, with a wide output frequency range.

• TSMC
• 180nm
• BCDG2
• Silicon Proven