PHY Transceiver IP Listing

The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps.

• Bluetooth
• Customizable on request
• Now
• IEEE 802.15.4

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.

• Single-Protocol PHY
• Serial ATA (SATA) I/II, Ser…

IP

• Single-Protocol PHY
• proven
• immediate

SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling.

• Single-Protocol PHY
• Please contact the provider for test chip availability
• now
• PCIe Base Specification 1.0…

MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…

• Multi-Protocol PHY

To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI®) Alliance was created to d…

• MIPI D-PHY

MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…

• Multi-Protocol PHY

The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.

• MIPI D-PHY

The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.

• MIPI C-PHY

The demand for multimedia features are pushing device manufacturers to integrate more peripherals such as multi-megapixel cameras…

• MIPI D-PHY + 1

Our MIPI-D-PHY IP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Sta…

• MIPI PHY

The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.

• Ethernet

The HARD_TEMAC described in this document has been designed incorporating the applicable features described in IEEE Std.

• Ethernet

The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…

• Single-Protocol PHY

KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits.

• Single-Protocol PHY
• NOW

It supports both USB 3.1 Gen1 and Gen2 with this PHY IP.

• UMC
• 28nm
• HPC
• In Production

The USB 2.0 PHY IP Core is a solution for the physical layer (PHY) that prioritizes both high performance and low power consumpti…

• SMIC
• 40nm
• LL
• In Production

High RF performance at the lowest cost The icyTRX-LE-22 RF transceiver PHY IP delivers an optimal trade-off between power consump…

• Bluetooth

Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compli…

• PCI Express

A RF Transceiver (IP/die) for adding Bluetooth Low Energy v5.2 (2.4GHz) capability to any SoC with embedded MCU via a standard SP…

• TSMC
• 40nm
• G
• In Production