802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
Implementation of the new WLAN security standard 802.11i requires the NIST standard AES cipher in CTR and CBC modes (a.k.a.
- AES
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
802.11i CCM (CTR+CBC) AES Core for WiFi WLAN
Implementation of the new WLAN security standard 802.11i requires the NIST standard AES cipher in CTR and CBC modes (a.k.a.
TRC3114 is a Quad SerDes used as four independent 3.125Gb/s FC, BP, or cable transceiver or 10Gbps XAUI Transceive.
The D16450 is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450.
Configurable UART with FIFO and hardware flow control
The D16750 is a soft Core of a Universal Asynchronous Receiver / Transmitter (UART), functionally identical to the TL16C750.
The D16550 is a soft Core of Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C550A.
802.11 a b and g IEEE Standard - Wireless LAN
The MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards.
The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Informatio…
AES Multi-purpose crypto engine
The AES Multi-Purpose crypto engine includes a generic and scalable implementation of the AES algorithm and a configurable wrappe…
The D8254 is a programmable interval timer/counter, binary compatible with the 82C54 industry standard.
Basic CAN Protocol Controller Core
The Controller Area Network (CAN) bus, originally developed for the car industry, is a fast, reliable and cost-effective data bus…
I2C Bus Interface Slave -Base version
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmissio…
Slave I2C bus controller with FIFO
The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus.
The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission…
TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
This specific IP macro is designed in TSMC 7nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
This specific IP macro is designed in TSMC 65nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
This TSMC 3nm 1.8V, 1.2V and 0.9V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
This TSMC 3nm 3.3V ESD Local Clamp provides compact, low-capacitance on-chip ESD protection for sensitive I/O and interface pins.
TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
This TSMC 3nm 1.2V ESD Local Clamp provides low-capacitance, low-leakage on-chip ESD protection for sensitive I/O and high-speed interface pins.
TSMC 22nm 5V5 ESD Power Clamp – Low Leakage
This TSMC 22nm 5.5V ESD Power Clamp provides low-leakage protection for sensitive supply and interface pins.
This specific IP macro is designed in TSMC 12nm and can be ported to other technologies upon request using Sofics in-house design tool flow.