DCD-SEMI Introduces eSPI Combo for Next-Generation Intel-Based Platforms
DESPI eSPI Controller IP Core and DESPI eSPI IP Core Target deliver a complete, high-speed eSPI interface solution for FPGA and ASIC designs.
Vendor:
Digital Core Design
Category:
I2C / I3C
I2C Bus Interface Slave -Base version
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmissio…
Overview
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can work as a slave receiver or as a transmitter - depending on the working mode, determined by the master device. A very simple interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by the I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast and High Speed.
The DI2CS is a technology independent design which can be implemented in a variety of process technologies.
The DI2CS is a technology independent design which can be implemented in a variety of process technologies.
Key features
- Conforms to v.3.0 of the I2C specification
- Slave operation
- Slave transmitter
- Slave receiver
- Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Allows operation from a wide range of input clock frequencies
- Support for reads, writes, burst reads, burst writes, and repeated start
- 7-bit addressing
- No programming required
- Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Benefits
- Getting a sillicon proven IP
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Technological independence (VHDL and Verilog)
- Global sales network
- Professional service
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Specifications
Identity
Part Number
DI2CSB
Vendor
Digital Core Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
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Frequently asked questions about I2C / I3C IP cores
What is I2C Bus Interface Slave -Base version?
I2C Bus Interface Slave -Base version is a I2C / I3C IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.