Configurable UART with FIFO and hardware flow control

The D16750 is a soft Core of a Universal Asynchronous Receiver / Transmitter (UART), functionally identical to the TL16C750. The D16750 allows serial transmission in two modes - UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing up to 512 bytes (plus 3 bits data error per byte in the RCVR FIFO) to be stored, both in receive and transmit directions. Our trustworthy core performs serial-to-parallel conversion on data characters, received from a peripheral device or from a MODEM, and a parallel-to-serial conversion on data characters, received from the CPU. The CPU can read acomplete status of the UART at any time, during the functional operation. The reported status information includes the type and condition of the transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt).
The D16750 includes a programmable baud rate generator, which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic.
What's more important, our revolutionary core has a complete MODEM control capability and a processor-interrupt system. Thanks to it, interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communication link. The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency. The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and FIFO's or change the FIFO's size. So, in applications with an area limitation and where the UART works only in the 16450 mode, disabling Modem Control and FIFO's, allow to save about 50% of logic resources.
The core is perfect for applications, where the UART Core and a microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices.
Thanks to a universal interface, the D16750 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
Moreover, we have implemented a selectable autoflow control feature in the FIFO mode. What does it mean for you? Thanks to this useful feature, you can significantly reduce software overload and increase system efficiency. It'll be done automatically by controlling serial data flow through the RTS output and the CTS input signals.

The D16750 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our core is a technology independent design, that can be implemented in a variety of process technologies.