Overview
The D16450 is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450. It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The CPU can read a complete status of the UART at any time during the functional operation. Reported information status includes a type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16450 includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive receiver logic. Our proprietary solution also has a complete MODEM control capability and processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communication link. A separate BAUD CLK line allows to set an exact transmission speed, while UART internal logic is clocked with CPU frequency. The core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Our solution is also dedicated for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to the D16450 universal interface, both core implementation and verification are very simple. They can be simply done by eliminating a number of clock trees in the complete system. The D16450 includes a fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our trustworthy solution is a technology independent design, which can be implemented in variety of process technologies.
Learn more about UART IP core
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