DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process.
- DLL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DDR DLL IP, Input: 100MHz - 200MHz, Output: 100MHz - 200MHz, UMC 0.162um LL process
Input 100M-200MHz, output 100M-200MHz, DDR DLL, UMC 0.162um Logic process.
Band Gap IP, Input: 2.0V - 3.6V, VBG=1.22V, UMC 0.153um MS process
Input 2.0V-3.6V, VBG=1.22V, Band Gap, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process.
D/A Converter IP, 10 bits, 44Msps, UMC 0.162um SP process
10-Bit 44MSPS current output dual channel Digital-to-Analog converter, UMC 0.162um Mixed-Mode Logic process.
D/A Converter IP, 10 bits, 1MHz, UMC 0.153um MS process
10-Bit 1MHz Voltage Output R-2R Digital-to-Analog converter, UMC 0.153um Logic/Mixed-Mode process.
D/A Converter IP, 10 bits, 150Msps, UMC 0.153um SP process
10-Bit 150MSPS current output differential-end Digital-to-Analog converter, UMC 0.153um Mixed-Mode/Logic process.
Audio ADDA IP, 16 bits, Audio Codec, UMC 0.162um G2 process
16-Bit Audio CODEC DA + 5-Bit SAR AD (The enhancement of FXADDA1623HA0A), UMC 0.162um GII Logic process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process
24-Bit 96KHz Sampled Mono Audio CODEC with Speaker Driver, UMC 0.153um Logic/Mixed-Mode process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process
24-Bit 96KHz Sampled Mono Audio CODEC with Speaker Driver, UMC 0.153um Logic/Mixed-Mode process.
Audio ADDA IP, 24 bits, 96KHz, UMC 0.153um SP process
24-Bit 96KHz Sampled Mono Audio CODEC with Speaker Driver & Microphone bias, UMC 0.153um Logic/Mixed-Mode process.
A/D Converter IP, 6 bits, 85Ksps, UMC 0.162um G2 process
6-Bit 85KSPS 2-to-1 single-end Analog-to-Digital converter, UMC 0.162um GII Logic process.
A/D Converter IP, 10 bits, 40Msps, UMC 0.162um SP process
10-Bit 40MSPS 2-channel Differential Analog-to-Digital converter, UMC 0.162um Mixed-Mode Logic process.
A/D Converter IP, 10 bits, 1Msps, UMC 0.153um SP process
10-Bit 1MSPS single-end Analog-to-Digital converter with 8-to-1 Mux, UMC 0.153um Logic/Mixed-Mode process.
0.1 to 1 GHZ Frequency Divider
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USB 2.0 HUB - Hub PHY, 1upstream /4 downstream
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