AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP

For six decades, Moore's geometric scaling drove progress in semiconductors. That industry compact no longer holds: returns from pure dimensional shrinking have flattened, leading-edge design budgets exceed one billion dollars per chip, and cost-per-transistor at the most advanced nodes is no longer falling.

This paper describes a CSoC platform and configurable digital subsystem IP which can be deployed for development of IOT edge devices. The paper encompasses the different attributes of IOT edge device that can cater multiple industry segments, key features and benefits of CSoC platform, components of the digital subsystem IP that enables rapid prototyping of SoCs for IOT applications.

Secure System-on-Chips (SoCs) based on ARM® TrustZone® technology enable both hardware and software components to be isolated as a secure subsystem within a complex SoC and as such focus on processing protected, sensitive and valuable assets, such as payment credentials, whenever these might be endangered with an attack, modification or capture. At the same time the main system software may be an open Rich OS platform that enables downloading and use of arbitrary third-party and non-trusted applications which can gain access to almost all system hardware elements.

The technique that has the highest impact on verification is perhaps the most widely used: power shut off (PSO). Shutting off functional units not currently needed clearly saves both leakage current and dynamic power.

This paper discusses how DesignWare VIP for OCP helps you test the spread of best-case, worst-case memory response.