Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device high frequency crystal osc IO Library.
- Analog
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Specialty OSC IO IP, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process 1.8V device high frequency crystal osc IO Library.
Specialty Analog ESD IO IP, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process 1.8V Analog ESD io Cell Library.
General Purpose IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process mini IO (blown up version of 0.18u Mini-IO).
General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process
UMC 0.162um GII Logic process true 3.3V standard BOAC IO Cell Library (0.18um shrink process).
General Purpose IO IP, BOAC (Bonding Over Active Circuit), UMC 0.162um G2 process
UMC 0.162um GII Logic process True 1.8V IO cells.
DDR2/3 Combo SDRAM Controller.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.162um G2 process
UMC 0.162um GII Logic process high density Core Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.153um MS process
UMC 0.153um Mixed-Mode/Logic process Mini-Library.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.153um LL process
UMC 0.153um Mixed-Mode/Logic process Generic Core Cell Library.
Voltage Detector IP, 4 Levels, UMC 0.153um G2 process
4-level detector for USB-OTG, VCCA=3.3V, Ivcca=125uA, UMC 0.153um 1.8V/3.3V GII Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.162um Logic process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.162um Logic process.
Linear Regulator IP, Output: 1.8V/150mA, UMC 0.153um MS process
3.3V to 1.8V LDO regulator with 150mA driving.Iq=66uA, UMC 0.153um Mixed-Mode/Logic process.
Linear Regulator IP, Output: 4.2V/1000mA, UMC 0.153um MS process
5.0V to 4.2V Linear Regulator with 1000mA driving capability, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode process.
DC-DC IP, Input: 3.3V, Output: 3.3V/300mA, UMC 0.153um MS process
5.0V to 3.3V high efficiency converter with 300mA driving capability PWM Regulator, UMC 0.153um 1.8V/3.3V Logic/Mixed-Mode proces…
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 0.153um MS process
Pulse Width Modulation, boosting voltage from 3.3V to 5V/50mA driving capability, Ivcca=140uA@Idrive=0, UMC 0.153um Logic/Mixed-M…
Power on Reset IP, Input: 1.8V, UMC 0.162um Logic process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.162um Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 0.162um LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 0.162um Logic process.
PLL IP, Input: 32.768KHz, Output: 12MHz, UMC 0.153um G2 process
Input 32.768KHz, output 12MHz, PLL, UMC 0.153um GII Logic/MM process.
RC Oscillator IP, Output: 50MHz, UMC 0.162um G2 process
Internal-RC, frequency 50MHz.
RC Oscillator IP, Output: 40MHz, UMC 0.162um G2 process
Internal-RC, frequency 40MHz.