Actt
•
HQ:
China
IP
- SMIC
- 55nm
- LL
- Silicon Proven
Compare 863 SerDes IP Listing from 76 vendors
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V-Trans Microelectronics• HQ: CHINA
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
- Single-Protocol PHY
- please contact us
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V-Trans Microelectronics• HQ: CHINA
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
- Single-Protocol PHY
- please contact us
- now
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V-Trans Microelectronics• HQ: CHINA
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 con…
- Single-Protocol PHY
- now
-
V-Trans Microelectronics• HQ: CHINA
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
- Single-Protocol PHY
- please contact us
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V-Trans Microelectronics• HQ: CHINA
This transmitter converts 10 LVDS, (low voltage differential signaling) data streams, into up to 60 bits (dual pixel 30-bits) CMO…
- Single-Protocol PHY
- please contact us
-
V-Trans Microelectronics• HQ: CHINA
This receiver converts 10 LVDS, (low voltage differential signaling) data streams, into 30bits dual pixel CMOS data plus 10 contr…
- Single-Protocol PHY
- please contact us
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V-Trans Microelectronics• HQ: CHINA
V-Trans ‘s FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow …
- Single-Protocol PHY
- please contact us
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V-Trans Microelectronics• HQ: CHINA
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
- V-By-One
- OpenLDI ,LVDS IEEE Standard…
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V-Trans Microelectronics• HQ: CHINA
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
- V-By-One
- please contact us
- OpenLDI ,LVDS IEEE Standard…
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Serdes PHY - 1.25~5Gbps, compatible with SATAII, SAS, PCIe and SONET
IPGoal Microelectronics Co. Ltd.• HQ: ChinaIP
- Optical Transport
- Silicon Proven
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TaraCom Integrated Products, Inc.• HQ: USA
IP
- TSMC
- 90nm
- CIS
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Innosilicon Technology Ltd• HQ: China
The UALink IP supports 800Gbps and 400Gbps bandwidth modes with backward compatibility for 200Gbps and 100Gbps.
- Controller + 1
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1.6T Ultra Ethernet Controller
Cadence Design Systems, Inc.• HQ: USAMAC/PCS/FEC Solutions up to 1.6T
- Controller
- Ethernet 1.6T
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Mixel, Inc.• HQ: USA
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
- PHY
- ASA Motion Link
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Chip Interfaces ApS• HQ: Denmark
Early adopter version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters The JESD204E Contro…
- JESD204
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Universal Serial 10GE Media Independent Interface (USXGMII)
Comcores• HQ: DenmarkThe USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
- Single-Protocol PHY
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Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- TSMC
- 28nm
- HPC+
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Low Power PCIe Gen3 PHY on TSMC CLN16FFC
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- TSMC
- 16nm
- FFC
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Low Power PCIe Gen3 PHY on TSMC CLN12FFC
Analog Bits Inc.• HQ: USAThe Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- TSMC
- 12nm
- FFC