DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
- Channel Coding
- now
- DOCSIS 3.1 standard
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
2 mA LDO voltage regulator (output voltage 1.2 V)
The voltage regulator consists of a differential amplifier, pass transistor and resistor's divider.
CSI-2 transmitter controller for application processor
The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC an…
Controller Area Networks, CAN 2.0B Bus Controller IP Core
CAN is part of HCL’s IP offerings and supports Version 2.0, PART B specification released by Bosch.
IP is a low power high resolution RC oscillator nominally operates at 100 MHz output clock from a 1.2 V supply.
IP is a low power high resolution RC oscillator nominally operates at 10 MHz output clock from a 1.2 V supply.
The block consists of voltage detector, power on reset and NOR3 gate.
IP is a low power high resolution RC oscillator nominally operates at 1.024 MHz output clock from a 1.2 V supply.
065TSMC_PoR_02 is a Power-on-Reset (PoR) circuit provides a reset signal to the chip when supply voltage reach required level.
Video De-Interlacer converts the interlaced video signals into non-interlaced signals.
Color Space Converter converts video data from one color space format to another format.
Chroma Re-sampler core can be used as chroma sub sampling or chroma up sampling.
Video Scaler converts the video signals from one resolution to another resolution.
Video Encoder Interface core accepts unformatted video data (without blanking/synchronization information) in 10-bit Y’CbCr 4:2:2…
LCD/HDMI Video Output Interface
LCD/HDMI Video output Interface supports various display modes and programmable display sizes.
Alpha Blender is used when two video sources have to be viewed at the same time.
sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards.
iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0.
SDIO Slave controller facilitates the design of SDIO cards and reduces the development time.