Overview
CAN is part of HCL’s IP offerings and supports Version 2.0, PART B specification released by Bosch. This IP supports standard FIFO interface at application side and standard interface that would get connected to CAN Transceiver. It offers a simple register interface for communication with host. This register interface can be customized quickly if needed, for other leading industry standard bus interface to host such as Avalon, AXI4 – Lite, AHB, and APB. This IP is efficient and functionally verified and well tested design for the CAN (Version 2.0, PART B) and can be immediately used in SoC designs in need of the CAN Interface.
Learn more about CAN / CAN-FD / CAN-XL IP core
In this paper, we explain how we adopted the post processing method to make sure we check for signatures that are expected are present in the log files. This acted as a safety net when engineers made inadvertent mistakes and introduced issues in the code base.
This paper deals with the implementation of UPF for low power SoC design that can encompass several vendor IPs and custom IPs UPF constraints.
This paper discusses about the low power IP components from ARM can help one to realize the low power features in the SoC. It should be noted that this paper does not discuss about the low power concepts or design techniques. Rather, it focuses on the implementation approaches using ARM low power IP.
In this paper we concentrate only on formal analysis using ‘model checking’. The model checking uses assertions (term broadly used to mean assertion, assume, restrict) written in System Verilog Assertions (SVA) language to prove the given design behavior. The focus of the paper is to provide an introductory flow of formal property check, however, the paper uses a real example to explain the flow.
Autonomous Vehicles (AV) needs more intelligence when it is on the move. The intelligence is not just an algorithm driven based on multiple sensor inputs alone, but here the intelligence need to be highly situational aware and by keeping the current vehicle dynamics. This needs lot situational and scenario based complex computation and communication with multiple Electronic Control Unit (ECU) within the vehicle.
Constrained random verification, for quite some time now, has been the default verification methodology for complex ASIC/SoC designs. Central to this methodology is the process of letting the randomization engine choose values from a set of possible values.
