Vendor: NTLab Category: Power On Reset (POR)

Power on Reset

065TSMC_PoR_02 is a Power-on-Reset (PoR) circuit provides a reset signal to the chip when supply voltage reach required level.

TSMC 65nm GP Silicon Proven View all specifications

Overview

065TSMC_PoR_02 is a Power-on-Reset (PoR) circuit provides a reset signal to the chip when supply voltage reach required level. The block generates reset signal depending of the level supply voltage with hysteresis. It includes bandgap with reference current and Power on Reset block.

Key features

TSMC CMOS 65 nm
Input voltage range: from 0.9 V to 1.3 V
Embedded power on reset module
Low quiescent current
Portable to other technologies (upon request)

Block Diagram

065TSMC_PoR_02 block diagram

Applications

Core voltage low battery indication
Supply voltage sensitive circuits
Battery-Powered equipment
Power solutions

What’s Included?

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Silicon Options

Foundry	Node	Process	Maturity
TSMC	65nm	GP	Silicon Proven

Specifications

Identity

Part Number

065TSMC_PoR_02

Vendor

NTLab

Type

Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab

HQ: Lithuania

Frequently asked questions about Power-On Reset (POR) IP cores

What is Power on Reset?

Power on Reset is a Power On Reset (POR) IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.