Asynchronous Communications Interface Adapter (ACIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
- UART
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Asynchronous Communications Interface Adapter (ACIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
Peripheral Interface Adapter (PIA)
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
16 bits sigma-delta ADC - UMC 0.18um
16 bits 40kS/s sigma-delta ADC.
Power-on reset for 1.8V. - UMC 0.18um
Power-on reset circuit monitoring 1.8V supply.
Low-noise bandgap reference - TowerJazz 0.18um
Low-noise bandgap reference
The multiplier operation is essential and abundant in DSP Applications.
Open source version of the UltraSPARC T1 processor
OpenSPARC T1 is the open source version of the UltraSPARC T1 processor.
Aliathon’s VT/TU Mapper performs the insertion and extraction of PDH signals into or from multiple VT/TU paths.
ADPCM (Adaptive Differential Pulse Code Modulation) is used for speech compression of 64 kbit/s PCM data.
Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rat…
Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz The …
The PLBv46 to PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 complian…
The Divider Generator LogiCORE™ IP provides a resource efficient and high performance solution for integer division.
XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 …
32-bit Initiator/Target for PCI Single Project Spartan Series
32-bit Initiator/Target for PCI™ Single Project Spartan® family enables designers to build a customized 32-bit system running at …
32-bit Initiator/Target for PCI
32-bit Initiator/Target for PCI™ enables designers to build a customized 32-bit system running at speeds up to 66 MHz that perfor…
32-bit & 64-bit Initiator/Target for PCI Product Bundle
DO-DI-PCI-AL rolls both the 32-bit and 64-bit Initiator/Target for PCI™ LogiCORE™ IP cores together into one convenient bundle.
The Distributed Memory Generator is provided under the terms of the Xilinx End User License and is included with ISE® and Vivado™…
The extended dynamic range and precision offered by floating-point arithmetic is quickly becoming a requirement in numerous signa…
The OPB to PCI 32/33 Bridge is offered as an evaluation core in the EDK.