Embedded Tri-mode Ethernet MAC Wrapper
The CORE Generator™ Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper file…
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Embedded Tri-mode Ethernet MAC Wrapper
The CORE Generator™ Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper file…
A Free parameterizable core that can be used with Gigabit Ethernet MAC, soft and Embedded Tri-Mode Ethernet MAC Cores.
Microchip Technology™ PIC16C5x 8-bit micro controller
The IP-AL16C5x core is the VHDL model of the Microchip Technology™ PIC16C5x 8-bit micro controller.
IP-ALFFT soft core is the unit to perform the Fast Fourier Transform (FFT).
Instruction Set Compatible with the 8052 8-bit Microcontroller Architecture
IP-AL8052S soft core is instruction set compatible with the 8052 8-bit microcontroller architecture and can achieve average perfo…
USB Function Controller, Fully Compatible with USB 2.0
USB core is the VHDL model of USB Function Controller, which is fully compatible with the USB 2.0 specification.
Aliathon’s SONET/SDH Framer Core implements Transport Overhead framing functions for SONET/SDH links, including frame generation …
Aliathon’s OTN Framer Core implements OTU, ODU and OPU layer functions and provides an integrated Reed-Solomon FEC codec in a fle…
Aliathon’s Packet Classification core is targeted at replacing expensive & power hungry Network Processors (NPUs) and Content Add…
E1/T1 Line Interface Unit / Framer
Aliathon’s Multi-Channel E1/T1 Line Interface Core provides a flexible, resource-efficient, high-density programmable logic based…
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew…
The datasheet provides the design specification for the MicroBlaze Debug Module (MDM).
The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB.
The LMB module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems.
The Fixed Interval Timer (FIT) is a peripheral that generates a strobe signal at fixed intervals and is not attached to any bus.