Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Dolphin Technology
Category:
SRAM
Memory Compilers
Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the…
Overview
Dolphin provides a wide range of Memory Compilers and Specialty Memory (ROM, Multi Port RF, CAM, etc.) optimized to meet even the most demanding requirements for high performance, high density and low power.
The compilers enable SoC designers to generate macros with varying aspect ratios, redundancy schemes, VT variations and more.
| SRAM & RF CATEGORY | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55/65nm | 80/90nm |
| High Performance - uses high current bit cells for high performance | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢1,2 |
| High Density - uses high-density bit cells tominimize area profile | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢1,2 |
| Ultra Low Leakage - significantly reduces leakage power while retaining all memory contents | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢1,2 |
| Dual Rail - reduces active and leakage power (periphery and array are run at separate voltages) | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Power Gating - significantly reduces leakage power without retaining memory contents | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| SRAM & RF TYPE | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55/65nm | 80/90nm |
| Single Port SRAM - Up to 8K words deep, up to 288 bit wide, single instance up to 288 Kb | 🟢 | 🟢 | 🟢 | |||||
| Single Port SRAM - Up to 8K words deep, up to 320 bit wide, single instance up to 320 Kb | 🟢 | 🟢 | 🟢 | |||||
| Single Port SRAM - Up to 16K words deep, up to 288 bit wide, single instance up to 576 Kb | 🟢3 | 🟢3 | 🟢 | |||||
| Single Port SRAM - Up to 16K words deep, up to 320 bit wide, single instance up to 640 Kb | 🟢 | |||||||
| Pseudo Dual Port SRAM - Up to 8K words deep, up to 288 bit wide, single instance up to 288 Kb | 🟢 | |||||||
| Pseudo Dual Port SRAM - Up to 8K words deep, up to 320 bit wide, single instance up to 320 Kb | 🟢 | 🟢 | 🟢 | |||||
| Pseudo Dual Port SRAM - Up to 16K words deep, up to 320 bit wide, single instance up to 640 Kb | 🟢 | |||||||
| Dual Port SRAM - Up to 8K words deep, up to 288 bit wide, single instance up to 288 Kb | 🟢 | 🟢 | 🟢 | |||||
| Dual Port SRAM - Up to 8K words deep, up to 160 bit wide, single instance up to 160 Kb | 🟢 | 🟢 | 🟢 | |||||
| Dual Port SRAM - Up to 16K words deep, up to 144 bit wide, single instance up to 288 Kb | 🟢3 | 🟢3 | ||||||
| Dual Port SRAM - Up to 16K words deep, up to 160 bit wide, single instance up to 320 Kb | 🟢 | |||||||
| Dual Port SRAM - Up to 16K words deep, up to 288 bit wide, single instance up to 576 Kb | 🟢 | |||||||
| 1 Port RF - Up to 1K words deep, up to 288 bit wide, single instance up to 72 Kb | 🟢 | 🟢 | 🟢 | 🟢 | ||||
| 1 Port RF - Up to 1K words deep, up to 640 bit wide, single instance up to 160 Kb | 🟢 | 🟢 | 🟢 | |||||
| 1 Port RF - Up to 2K words deep, up to 640 bit wide, single instance up to 320 Kb | 🟢 | |||||||
| 2 Port RF - Up to 1K words deep, up to 288 bit wide, single instance up to 72 Kb | 🟢 | 🟢 | 🟢 | 🟢 | ||||
| 2 Port RF - Up to 1K words deep, up to 640 bit wide, single instance up to 160 Kb | 🟢 | 🟢 | ||||||
| 2 Port RF - Up to 2K words deep, up to 640 bit wide, single instance up to 320 Kb | 🟢 |
| SPECIALTY MEMORY | 2/3nm | 4/5nm | 6/7nm | 12/16nm | 22/28nm | 40nm | 55/65nm | 80/90nm |
| Read Only Memory Compilers - Via Programmable and Diffusion | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Content Addressable Memory Compilers - Binary BCAM, Ternary TCAM and CAM | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 | 🟢 |
| Specialty Memory - Custom Register Files (4R/1W, 4R/2W, 3R/3W, 8R/1W, 5R/3W, etc.) | 🟢R | 🟢R | 🟢R | 🟢R | 🟢R | 🟢R | 🟢R | 🟢R |
1 SRAM Without Redundancy 2 RF 2-Port (1R/1W) 3 LP & ULP nodes only R Upon Request
Specifications
Identity
Part Number
Memory Compilers
Vendor
Dolphin Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SRAM IP cores
What is Memory Compilers?
Memory Compilers is a SRAM IP core from Dolphin Technology listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.