Aliathon’s OTN Framer Core implements OTU, ODU and OPU layer functions and provides an integrated Reed-Solomon FEC codec in a fle…
- Optical Transport
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Aliathon’s OTN Framer Core implements OTU, ODU and OPU layer functions and provides an integrated Reed-Solomon FEC codec in a fle…
Aliathon’s Packet Classification core is targeted at replacing expensive & power hungry Network Processors (NPUs) and Content Add…
E1/T1 Line Interface Unit / Framer
Aliathon’s Multi-Channel E1/T1 Line Interface Core provides a flexible, resource-efficient, high-density programmable logic based…
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew…
The datasheet provides the design specification for the MicroBlaze Debug Module (MDM).
The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB.
The LMB module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems.
The Fixed Interval Timer (FIT) is a peripheral that generates a strobe signal at fixed intervals and is not attached to any bus.
The LogiCORE™ IP FIFO Generator core generates fully verified first-in, first-out (FIFO) memory queues ideal for applications req…
The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based D…
UMTS/3GPP Turbo Convolutional Encoder
This version of the Turbo Convolutional encoder is designed to meet the 3GPP specification.
The Interleaver/De-interleaver LogiCORE™ module is a high-speed, compact design that is fully synchronous, using a single clock.
Digital Clock Manager (DCM) Module
The Digital Clock Manager (DCM) primitive in Xilinx FPGA parts is used to implement delay locked loop, digital frequency synthesi…
The Xilinx LogiCORE™ CORDIC IP implements a generalized coordinate rotational digital computer (CORDIC) algorithm, initially deve…
The Xilinx® LogiCORE™ IP Convolutional Encoder core can be used in a wide variety of error correcting applications and is typical…