How to simplify power design development and evaluation for FPGA-based systems
Validation of power supply voltage at the FPGA; real-time monitoring of Vccint power consumption; realistic power estimates using accurate on-die temperature measurement.
Vendor:
Xilinx, Inc.
Category:
Register File
RAM-based Shift Register
The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew…
Overview
The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in Xilinx FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.
Key features
- Supports inputs ranging from 1 to 256 bits wide
- Supports shift register depth from 1 to 1088 for fixed-length or 1 to 1024 for variable-length sift registers.
- Speed or resource optimization for all modes with capability to specify optional output register.
- Instantaneous Resource Estimation
Specifications
Identity
Part Number
RAM-based Shift Register
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Register File IP cores
What is RAM-based Shift Register?
RAM-based Shift Register is a Register File IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Register File?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Register File IP.
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