TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- LV
TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015LV 150nm Deskew PLL - 140MHz-700MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015G 150nm Deskew PLL - 65MHz-325MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL015G 150nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
1.056GHz SSCG PLL on TSMC 40nm
Analog-PLL For Spread Spectrum Clock on TSMC 40nm
1.25GHz Multiplying PLL on TSMC 40nm
Analog-PLL For Frequency Multiplying on TSMC 40nm
1.68GHz Deskew PLL on TSMC 28nm
Analog-PLL For Skew adjust on TSMC 28nm
1.8GHz SSCG PLL (HPM/HPC) on TSMC 28nm
Analog-PLL For Spread Spectrum Clock on TSMC 28nm
1.4GHz Deskew PLL on TSMC 28nm
Analog-PLL For Skew adjust on TSMC 28nm
4GHz Fractional PLL on TSMC 28nm
Analog-PLL For Frequency Multiplying on TSMC 28nm
4.1GHz Multiplying PLL on TSMC 16nm
Analog-PLL For Frequency Multiplying on TSMC 16nm
5GHz-7.5GHz PLL in GF 22nm FDX
Ultra-low power, high SFDR ring-oscillator-based PLL-5GHz-7.5GHz in GF 22nm FDX