Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA.
- Channel Coding
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA.
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA Aurora is a LogiCORE™ IP designed to enab…
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…
Spartan-6 FPGA Integrated Endpoint Block for PCI Express (PCIe)
Xilinx provides a Spartan-6 FPGA Integrated Endpoint solution for PCI Express® (PCIe) to configure the Spartan-6 FPGA Integrated …
The Video Timing Controller LogiCORE IP is a general purpose video timing detector and generator.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Color Filter Array Interpolation
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is adde…
VeriSilicon SMIC 0.18μm 1.8V/3.3V CFIO_01 Library
VeriSilicon SMIC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for SMIC 0.18μm 1P6M Salicide logic proces…
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial…
VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
VeriSilicon SMIC 0.13μm SSTL2/SSTL18 Combo I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing…
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O 01C Library
VeriSilicon SMIC 0.13μm 3.3V Multiple I/O 01C Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing …
32-bit/33MHz Multi-Function PCI Master/Target
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification.
SMIC 0.18um 1.8v Ring Oscillator
The present IP is a Ring Oscillator.
SMIC 0.18um 1.8V/3.3V Power Switch
The SMIC18_PSW_02B is a 3.3V PMOS power switch connecting the main supply and the core area.
SMIC 0.18um 1.8V/3.3V Power Switch
The SMIC18_PSW_02 is a 3.3V PMOS power switch connecting the main supply and the core area.
SMIC 0.18um 1.8v APLL with Free Running
This IP is a programmable Analog PLL suitable for high speed clock generation.
To provide a solution to MMC cards, SMIC18_MMC_07E_4IN1 is consolidated by four independent IPs: SMIC18_PRG_03E_33T18V60_160mA, S…
SMIC 0.18um 1-Channel 12-bit 200K 3.3V Multi-Input SAR A
This analog-to-digital converter (ADC) is a one-channel SAR ADC with multi-input PGA and bandgap.