Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. Its high speed VCO can run from 100MHz to 250MHz. This IP has an important feature of free-running and supports three operation modes: PLL mode, free-running mode and bypass mode. When PLL is locked, the IP works as a simple PLL in PLL mode. By setting DM [2:0] and DN [5:0] to different values according to different REFIN, CLKO will be locked at the multiples of input frequency. But when PLL is un-locked (before locked or after input clock is lost), the IP works in free-running mode and CLKO will be generated by the internal ring oscillator (ROSC), outputting a frequency of 148MHz+/-30%. Once PLL is locked again, CLKO will change back to PLL frequency.
Learn more about PLL IP core
How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.
Jian Yang, Sween Kang (Synopsys)
This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
