Overview
This IP is a programmable Analog PLL suitable for high speed clock generation. Its high speed VCO can run from 100MHz to 250MHz. This IP has an important feature of free-running and supports three operation modes: PLL mode, free-running mode and bypass mode. When PLL is locked, the IP works as a simple PLL in PLL mode. By setting DM [2:0] and DN [5:0] to different values according to different REFIN, CLKO will be locked at the multiples of input frequency. But when PLL is un-locked (before locked or after input clock is lost), the IP works in free-running mode and CLKO will be generated by the internal ring oscillator (ROSC), outputting a frequency of 148MHz+/-30%. Once PLL is locked again, CLKO will change back to PLL frequency.
Learn more about PLL IP core
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