Xilinx, Inc.
•
HQ:
USA
The AXI Hardware ICAP enables an embedded microprocessor, such as MicroBlaze, to read and write the FPGA configuration memory thr…
- System Controller
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Xilinx, Inc.• HQ: USA
The AXI GPIO provides a general purpose input/output interface to the AXI ( eXtensible Interface) interface.
- GPIO
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Xilinx, Inc.• HQ: USA
The AXI Streaming FIFO allows memory mapped access to a AXI Streaming interface.
- FIFO / CAM
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Xilinx, Inc.• HQ: USA
The AXI Ethernet Lite MAC supports the IEEE Std.
- Ethernet
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AXI External Peripheral Controller
Xilinx, Inc.• HQ: USAThe AXI External Peripheral Controller (AXI EPC IP Core) supports data transfers between the AXI4 Interface and external synchron…
- System Controller
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AXI External Memory Controller
Xilinx, Inc.• HQ: USAThe AXI EMC ( Microcontroller Bus Architecture (AMBA®) extensible Interface (AXI) External memory controller) provides the contro…
- Controller
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Xilinx, Inc.• HQ: USA
The AXI Direct Memory Access (AXI DMA) IP provides high-bandwidth direct memory access between memory and AXI4-Stream-type target…
- DMA
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Xilinx, Inc.• HQ: USA
The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use wit…
- DMA
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Xilinx, Inc.• HQ: USA
The AXI BRAM Controller is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK) and Vivado™ IP Integrator…
- DMA
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Xilinx, Inc.• HQ: USA
The axi2axi_connector is a utility module for use in EDK to cascade two AXI Interconnect modules.
- Protocol Bridge
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Xilinx, Inc.• HQ: USA
The AXI ( eXtensible Interface) to APB ( Peripheral Bus) Bridge translates AXI4-Lite transactions into APB transactions.
- Protocol Bridge
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Triple-Rate SDI on Virtex-6 FPGAs
Xilinx, Inc.• HQ: USAThe Serial Digital Interface (SDI), is widely used in broadcast applications for the transport of uncompressed SD and HD digital …
- Video Transport
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10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
Xilinx, Inc.• HQ: USAThe LogiCORE, 10 Gigabit Ethernet backpane PCS/PMA (10GBASE-KR) has been bundled with the 10G/25G Ethernet PCS/PMA with FEC/Auto-…
- Single-Protocol PHY
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Xilinx, Inc.• HQ: USA
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…
- Interlaken
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Xilinx, Inc.• HQ: USA
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
- Channel Coding
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Xilinx, Inc.• HQ: USA
Xilinx provides a market DPD solution that reduces CapEx and OpEx Digital Pre-Distortion (DPD) is one of the most fundamental bui…
- Filters Transforms
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Xilinx, Inc.• HQ: USA
The 3GPP LTE Channel Estimator LogiCORE™ IP provides an optimized channel estimation function for the Physical Uplink Shared Chan…
- Channel Coding
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4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
Pico Semiconductor, Inc.• HQ: USAPSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
- TSMC
- 40nm
- G
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Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)
Pico Semiconductor, Inc.• HQ: USAPSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps.
- TSMC
- 40nm
- G
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Low noise PLL operating at up to 3.25GHz (90nm UMC)
Pico Semiconductor, Inc.• HQ: USAPSI3GRP_U9 is a low jitter PLL operating from 1GHz to 3.25GHz.
- UMC
- 90nm
- SP