The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
- Network-On-Chip
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Xilinx® LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped…
The AXI PCIe® Gen 3 core provides an interface between the AXI4 interface and the Gen 3 PCI Express (PCIe) silicon hard core.
The AXI MCDMA facilitates large data migration, offloading the task from the embedded processor.
The Xilinx® LogiCORE™ AXI AMM Bridge IP core connects Avalon bridge slave IPs with AXI interface masters.
7 Series Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI ™/PCI-X ™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI…
50G IEEE 802.3 Reed-Solomon Forward Error Correction
Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications.
The Xilinx® LogiCORE™ IP 40G/50G Ethernet solution provides a 40 Gigabit or 50 Gigabit per second (Gbps) Ethernet Media Access Co…
The LTE PUCCH Receiver LogiCORE™ IP core provides the receive functionality required for the LTE Physical Uplink Control CHannel …
32G Fibre Channel (32GFC) Reed-Solomon Forward Error Correction
The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) subl…
IEEE 802.3bj Reed-Solomon Forward Error Correction
Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise…
GLOBALFOUNDRIES 28nm SLP Multiple Power Supply IO library
Multiple power supply IO library for GF28nm low power 1.0v/2.5v process
SMIC 55nm LP Multiple Power Supply IO library
Multiple power supply IO library for SMIC55nm low power 1.2v/2.5v process
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
GLOBALFOUNDRIES 28nm SLP sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors.
GLOBALFOUNDRIES 65nm LVDS Transmitter
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
GLOBALFOUNDRIES 28nm CMOS 1-Channel 10-Bit 350Msps+ Current-Steering D/A Converter
This IP specifies a 3-channel 10-bit resolution, high performance, low power CMOS Digital-to-Analog Converter (DAC) which offers …