GLOBALFOUNDRIES 22nm FDSOI 1.8v/0.8v Power Regulator
The Power Regulator is to provide 0.8v power supplies which are regulated from the single 1.8v input supply.
- GlobalFoundries
- 22nm
- FDX
- Pre-Silicon
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
GLOBALFOUNDRIES 22nm FDSOI 1.8v/0.8v Power Regulator
The Power Regulator is to provide 0.8v power supplies which are regulated from the single 1.8v input supply.
This IP is a programmable Analog PLL suitable for high speed clock generation.
GLOBALFOUNDRIES 28nm SLP 2.5v/1.0v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Samsung 28nm FDSOI 1.8v/1.0v APLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
UOE is high performance and customizable UDP/IP hardware stack compliant with RFC 768 (for UDP) and RFC 791 (for IPv4)/RFC 2460(f…
GLOBALFOUNDRIES 28nm SLP 1.8v/1.0v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
GLOBALFOUNDRIES 22nm FDSOI 1.8v/0.8v PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolu…
The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors,…
Two Input to One Output MIPI CSI-2 Camera Aggregator Bridge
Many new applications such as augmented reality, depth perception and gesture recognition require multiple image sensor interface…
SubLVDS to MIPI CSI-2 Image Sensor Bridge
Most off-the-shelf Application Processors use industry standard interfaces such as MIPI CSI-2.
The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets …
Serial RapidIO 2.1 Endpoint IP Core
The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, hig…
Serial RapidIO - Physical Layer Interface
The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2.
Many digital systems use filters to remove noise, provide spectral shaping, or perform signal detection.
The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with …
RGB to MIPI DSI Display Interface Bridge
Most mobile displays use industry standard interfaces such as MIPI DSI for interface connectivity.
Reed-Solomon codes are used to perform Forward Error Correction (FEC).
Reed-Solomon codes are used to perform Forward Error Correction.
Quad SPI-3 to SPI-4 PHY Layer Bridge
The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and…