Vendor: Lattice Semiconductor Corp. Category: SPI / QSPI XSPI

SPI 4.2 MACO Core

The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets …

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Overview

The LatticeSCM SPI4 MACO™ IP core implements an industry standard SPI4.2 interface used to transfer both variable length packets and fixed cell sizes between PHY and Link Layer devices in telecom and datacom applications. This flexibility makes it an attractive interface for Ethernet, SONET and ATM applications. Until now, this popular interface was only available as soft IP in FPGAs. The LatticeSCM device implements this core in an optimal combination of hard and soft gates to reduce the size of the core, reduce power and enhance user flexibility. Specifically, the Data Path is implemented in hard logic while the Status path is implemented in soft gates to enable designers to implement their own calendaring or prioritization schemes if they so choose.

Software Requirements

* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file

Key features

  • Fully compliant with OIF-SPI4.02.0 Specification
  • Supports up to 256 logical ports
  • 700 Mbps operation in Static Mode
  • 1+ Gbps operation in Dynamic Mode
  • Transmit/Receive Data Path
    • 16 bits wide, in-band port address, SOP, EOP indication, error control
    • LVDS I/O (IEEE 1596.3 – 1966 [1], ANSI/TIA/EIA-644-1995[2]
    • Source synchronous double edge clocking at 311MHz minimum
  • Static and Dynamic Alignment Modes
    • Up to 1 Gbps Dynamic Phase Alignment
    • Up to 700 MHz Static Alignment
    • Additional Quarter Rate Mode for sub 10G traffic
  • Transmit/Receive FIFO Status
    • 2 bit parallel FIFO status indication, in-band Start of FIFO status
    • LVTTL I/O or optional LVDS I/O (IEEE 1596.3)
    • Source synchronous clocking
  • Various run-time user controls:
    • Individual receiver/transmitter resets
    • De-skew only reset, AIL only reset
    • Force idles (transmitter)
    • Enable/Disable Packing (transmitter)
    • Training Pattern (CAL_M, MAX_T) Programmable burst modes to support NPU requirements
  • Link Layer Buffer Management Options (NEW):
    • Shared or per-channel buffer manager
    • Up to 16 separate physical FIFOs per Tx/Rx direction
    • Transmit Bandwidth Manager and Receive Channel Mapper
    • Parameterizable packet overflow and packet error drop
    • Graceful packet overflow drop
    • Both store & forward as well as cut-through operation
    • Parameterizable independent buffer depth per transmit and receive direction
    • Per channel empty, almost empty, full and almost full status
    • Programmable almost empty and almost full thresholds per channel
    • Dynamic channel provisioning
    • Programmable sequencer based scheduler.
  • Supported by System Bus and Serial Memory Interface (SMI) for in-circuit controllability
  • Pre-engineered hard cores using MACO technology to conserve power, FPGA resources and designer time
  • Multiple SPI4 IP core support per device
  • Supported in Windows, Linux, or Unix based tool flows
  • Supports both Verilog and VHDL tool flows

Block Diagram

SPI42MACO block diagram

Specifications

Identity

Part Number
SPI42MACO
Vendor
Lattice Semiconductor Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Lattice Semiconductor Corp.

Learn more about SPI / QSPI XSPI IP core

Frequently asked questions about SPI / QSPI / xSPI IP cores

What is SPI 4.2 MACO Core?

SPI 4.2 MACO Core is a SPI / QSPI XSPI IP core from Lattice Semiconductor Corp. listed on Semi IP Hub.

How should engineers evaluate this SPI / QSPI XSPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SPI / QSPI XSPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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