The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…
- I2S
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…
Converts Avalon Master Endpoints to AXI for seamless interconnection and integration
Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…
1G/10G/25G Switching Ethernet Subsystem
The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G phys…
IP
IP
IP
IP
IP
IP
IP
Rambus Circuit Camouflage Technology (formerly Inside Secure), also known as SecureMedia Library (SML), is an anti-reverse engine…
LTE Release-9 UE Protocol Stack (L2-L3) SW IP
The 3GPP Release 9 compliant LTE UE Protocol Stack SW IP is a Category 4 UE solution.
TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time …
Lossless & Near-Lossless JPEG-LS Encoder
The JPEG-LS-E core implements a efficient, low-power, lossless and near-lossless image compression engine that is compliant to th…
5.0V Programmable Gain Amplifier
The L7SPGA4B10G IP is programmable gain amplifier (PGA), which consists of single ended amplifier, input and output switches, 14-…
Lossless & Near-Lossless JPEG-LS Decoder
The JPEG-LS-D core implements a efficient and low-power, lossless and near-lossless image decompression engine that is compliant …
IP
IP
Clock latched comparator for 2V supply and PMOS type input designed in 0.18um 6M TSMC technology.
IP