Vendor: Naneng Microelectronics Category: Single-Protocol PHY

USB3.0/PCIE2/SATA3 Combo PHY

Key features

  • Support multiple-lane application
  • Fully comply with PIPE3 interface specification
  • Support 2.5 G, 5G serial data rate in PCIe application
  • Support 5.0G serial data rate in USB application
  • Support 1.5 G, 3.0 G and 6.0G serial data rate in SATA application
  • Parallel interface configurable to 40/32/20/16 bits respectively
  • Flexible reference clock input, with low frequency reference clock support
  • Fractional-N PLL with high resolution frequency program capability
  • Phase lock loop out of lock indicator
  • Low power mode control according to PCIE/USB specification
  • Receiver detection function in PCIe/USB mode
  • Support LFPS transmitting and receiving in USB3.0 mode
  • OOB/Beacon transmitting and receiving in SATA/PICE mode
  • Programmable Transmitter pre-emphasis and de-emphasis
  • Fully compatible to PCIE2/USB3/SATA3 electrical specification

Applications

  • Storage
  • PC
  • Multi-media

Specifications

Identity

Part Number
USB3.0/PCIE2/SATA3 Combo PHY
Vendor
Naneng Microelectronics
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 3.0

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB3.0/PCIE2/SATA3 Combo PHY?

USB3.0/PCIE2/SATA3 Combo PHY is a Single-Protocol PHY IP core from Naneng Microelectronics listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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