USB2.0 Dual-Role PHY, TSMC 55EF
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
- USB 2.0
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB2.0 Dual-Role PHY, TSMC 55EF
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB2.0 Dual-Role PHY, TSMC 12E, N/S orientation, type-C
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
BCH Encoder and Decoder IP Core
The IP Core implements BCH Code encoding and decoding.
The PCIe Gen4.0 PHY IP offers a low-power, compact solution with proven performance and robust signal and power integrity, making…
The PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations.
Logic Fruit Technologies has developed an ARINC 818-3 Transmitter & Receiver IP Core, supporting line rates up to 28 Gbps.
Highest performance Six-wide, RVA23, CHI bridge, RAS Functionality, Scalable to 256 cores
The highest performance P870-D is targeted for datacenter applications which benefit from parallelism, including storage, web ser…
3.3V to 1.8V and 0.9V step-down DC-DC converter
3.3V to 1.8V and 0.9V step-down DC-DC converter
8-bit, 1MSPS low-noise high accuracy analog-to-digital converter
The 8-bit, 1Msps ADC is a single-ended cyclic ADC based on 1.5-bit/conversion architecture with error correction.
AES encryption transforms plaintext into ciphertext through multiple transformation rounds.
Low-Power Design for Multi-Display and High Quality Image Processing
Single Port High Speed SRAM Memory Compiler on N22ULL
Single port SRAM compiler with low power retention mode.
Dual Port (1 read only port, 1 write only port) Register File Compiler on N22ULL
Two port register file (1R1W) with low power retention mode Bit Cell Power Supply (V) 8T 0.9
Single Port Register File Compiler on N22ULL
Single port register file compiler with low power retention mode Bit Cell Power Supply (V) 6T 0.9
Single Port Low Voltage SRAM Memory Compiler on N22ULL - Low Power Retention and Column Repair
Single Port SRAM Compiler with Low Power Retention Mode and Ultra Low Leakage Bit Cell Power Supply (V) 6T 0.9
Single Port Low Voltage SRAM Memory Compiler on N22ULL
Single port SRAM compiler with low power retention mode.
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
CSI-2 RX IP supports both C-PHY v1.2 and D-PHY v2.0 interfaces, enabling flexible integration across a wide range of image sensor…
The DSC Decoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.
The DSC Encoder IP supports visually lossless compression for high-resolution display systems, compliant with VESA DSC 1.2b.