The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
- SPI / QSPI XSPI
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The SPI (Serial Peripheral Interface) is a specialized communication interface targeting single, dual or quad SPI Flash memories.
Direct Memory Access Controller
The uDMA (Micro Direct Memory Access) controller serves as a hardware approach for direct data transfers between peripherals/memo…
SD Card Input/Output Protocol Controller
SDIO protocol is evolved and upgraded from the SD card protocol.
The Neural-Network Accelerators (NACC) improves the inference performance of neural networks.
The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion…
SLI UHS-II PHY Analog IP consists of a mixed-signal SERDES supporting both Full Duplex and Half Duplex modes.
Ethernet Switch VLAN 5x100M
Ethernet Switch/Router L2/L3/MPLS 12x10G
This L3 Ethernet Switch/Router IP core is built around a shared buffer memory architecture providing wire-speed switching and rou…
Ethernet Switch/Router Enterprise 9x10G + 2x25G
This is a L2 switch and an IP/MPLS router with ACL engines.
Ethernet Switch/Router Datacenter ToR 32x100G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 32 ports, with up to 100 Gbit of bandwidth per port.
Ethernet Switch/Router IPSec/MACSec 9x10G + 2x40G
This L2/L3 Ethernet Switching/Routing Core offers full wire-speed on all 11 ports.
The USB device core is compliant with revision 1.1.
Protocol controller IP for a CAN FD light responder node
The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.It supports CAN FD light respon…
Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
The XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, o…
Safety Enhanced GPNPU Processor IP
Automotive applications are uniquely demanding for any AI acceleration solution.
The Network on Chip (NOC) technology redefines typical NOC capabilities as it extends the on-chip network beyond chip(let) bounda…
USB Full Speed Transceiver
PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…