NVM MTP ULP TSMC 180nm CM018RI 3.3V
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
- TSMC
- 180nm
- BCDG2
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
NVM MTP ULP TSMC 180nm CM018RI 3.3V
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
NVM MTP ULP TSMC 180nm G 3.3V 125C Operation
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
NVM MTP ULP SilTerra 180nm G 3.3V
The Synopsys Multi-Time Programmable (MTP) Ultra-Low Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increa…
Synopsys Medium Density Non-Volatile Memory (NVM) IP, an alternative to embedded flash memory, provides up to 256 Kbits of on-chi…
NVM FTP Trim TowerJazz 180nm SL 3.3V
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
NVM FTP Trim TSMC 180nm G 3.3V
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
NVM FTP Trim TSMC 180nm BCDG2 5V
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
NVM FTP Trim TSMC 180nm BCDG2 5V ONLY
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
NVM FTP Trim TSMC 130nm G 3.3V
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
NVM FTP Trim SMIC 180nm G 3.3V
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
The Synopsys Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP provides the capability of reprogrammable NVM in a sta…
High-precision 16-bit complex digital up-converter / IQ modulator (DUC) with a fully configurable interpolation filter stage.
Flexible Pixel Processor Video IP
The PP300 IP, is a flexible Pixel Processor that provides a wide range of processing functions.
The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the features and benefits of A…
SerDes Hard Macro-IP in GlobalFoundries 22FDX
The SerDes Hard Macro-IP in GlobalFoundries 22FDX is an Off-the-Shelf IP.
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …