Vendor: FastVDO LLC Category: Video Processing

H.264 / AVC Baseline Main and High profile decoder

FV264 is a customizable ASIC IP for decoding H.264 compliant streams.

Overview

FV264 is a customizable ASIC IP for decoding H.264 compliant streams. H.264 decoder ASIC IP overcomes the limitations of DSPs and other processors based solutions that support limited resolutions and consume lot of power.
FV264 is easy to incorporate in any existing or new SOC or media processors. The core is customizable and is completely compliant to Baseline or main profile. The core has been prototyped on Xilinx Virtex4 based FPGA board for complete functionality.

Key features

  • Decoder Core is completely pipelined hardware architecture and does not use any processor or DSP cores.
  • Single S-RAM, SD-RAM or DDR-RAM required. Core can have independent or high speed shared memory
  • Synchronous single clocked design and low power architecture
  • Minimal processing required from host CPU. Core can be fully autonomous or stream can be fed through the host
  • Supports various resolutions from sub QCIF to HD and the core is customizable to provide optimal performance in power consumption
  • Supports both entropy coding techniques (CAVLC and CABAC)
  • Supports all modes of intra and inter prediction techniques with up to quarter pixel interpolation
  • Supports interlace decoding and in loop de-blocking filter
  • IP core is prototyped on a Xilinx FPGA and provide real time verification of the decoder
  • Ideal for mobile processors, set-top boxes, handheld devices, media processors all low power and compact multimedia SOCs
  • FastVDO can extend design services and tool support for integration of the decoder IP core

Benefits

  • Complete hardware implementation
  • Low-power
  • Cost-effective
  • easy integration
  • FPGA prototyped

Specifications

Identity

Part Number
FV264
Vendor
FastVDO LLC
Type
Silicon IP

Compute

Codec Standard
H.264 / AVC

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.264 / AVC Baseline Main and High profile decoder?

H.264 / AVC Baseline Main and High profile decoder is a Video Processing IP core from FastVDO LLC listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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