Standard Definition Video (PAL/NTSC) De-Interlacer, Advanced Algorithm
The xc-SDDIA core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used …
- Video Processing
- FPGA
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Standard Definition Video (PAL/NTSC) De-Interlacer, Advanced Algorithm
The xc-SDDIA core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used …
High-performance Low-memory Mixed Radix FFT
This FFT is an efficient implementation of the Decimation in Frequency (DIF) Cooley-Tukey FFT.
1KB/ECC40 NAND Flash BCH Encoder/Decoder
The BCH encoder/decoder provides error correction code (ECC) capabilities for applications such as data storage and transmission.
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706,…
This is a high performance pipelined implementation of AES optimized for encryption of uncompressed video on low cost FPGA famili…
The Helion SNOW3G core efficiently implements the stream cipher used as the basis for the UEA2 confidentiality algorithm and UIA2…
Certified USB 5G & 10G Host Controller
USB 5G, 10G Host controller is a configurable core and implements the USB Host functionality that can be interfaced with third pa…
Certified USB 5G & 10G, USB2 Hub controller
USB 5G, 10G and 2.0 Hub controller is a configurable core and implements the USB Hub functionality that can be interfaced with th…
Dual FPD-link Transmitter, 24 Bits Color, 20-170 Mhz (SVGA/UXGAW/Full HDTV)
Now available up to 170 Mhz per channel !
High Performance DTMB (GB20600-2006) Demodulator Core
Digital demodulator fully supporting GB20600-2006 China DTV standard.
The ntG711_CMP core implements the ITU G.711 compliant compressing.
The AES-IP-39 (EIP-39) is IP for accelerating the AES symmetric cipher algorithm (FIPS-197), supporting all NIST modes including …
The AES-IP-37 (EIP-37) is IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394) up to 6 Gbps.
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm.
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent tr…
The TC4500 Core complies with DVB-T2 specifications.
Rabbit (TM) 6000 microprocessor
Fifth generation Rabbit Microprocessor
Full-featured 16-bit counter/timer
Full-featured Async/Clocked Serial channel
Dual-channel 8/10 bit Quadrature decoder
Dual-channel 8/10 bit quadrature decoder