Baseline Profile H.264 Encoder
The H264-BP-E core is an self-contained hardware H.264 encoder that conforms to the ITU-T H.264 Constrained Baseline Profile.
- H.264 / AVC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Baseline Profile H.264 Encoder
The H264-BP-E core is an self-contained hardware H.264 encoder that conforms to the ITU-T H.264 Constrained Baseline Profile.
Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
The UHT-JPEG-D core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed t…
Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
The UHT-JPEG-E core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG encoder, with optio…
AES Encryption & Decryption IP Core − Programmable Block Cipher Modes
The AES-P IP core implements the FIPS-197 Encryption Standard.
SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators
The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2…
The Kasumi-IP-06 (EIP-06) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as…
SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators
HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algor…
Flexible and Silicon proven Ethernet Layer 2 Security solution The MACsec IP provides Ethernet Layer 2 Security for port authenti…
NFC Semiconductor IP - Combo (digital & analog)
Crossborder Technologies Korea supplies IP of NFC Controller IC.
1.2V Low Voltage Detector (LVD), Fujitsu 90nm
The AR22F01 is a mass-production proven low voltage detector (LVD) IP.
Cap-less 100mA Low Noise LDO, XFAB 250nm
The LDO is capable of outputting 1.2V voltage with maximum power of 100mA and low drop out voltage of less than 200mV.
Cap-less 25mA Low Noise LDO, Fujitsu 90nm
The AR25F01 is a mass-production proven cap-less LDO IP.
Aurora-like 8b/10b @3Gbps for ALTERA Devices
REFLEX CES introduces the industry’s first release of its Aurora-‐like IP Core based on ALTERA FPGA enabling interoperability be…
Multi-2 Descrambler Supporting BCAS for ISDB-T,TMM in Japan
MEGACAST MULTI2 IP core implements the MULTI2 encryption/decryption algorithms as specified by ISO9979/0009 algorithm register en…
BAYER_TO_RGB is a fully pipelined Bayer-mapped to RGB converter IP Core.
High Speed Low Power JPEG Codec IP Core
High Speed Low Power JPEG Codec IP Core
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
The VMESmodule is a VME Slave Controller core bridging the VME bus and the local bus.
Extensible Framework (EFW) For Xilinx KC705 Module
Extensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface c…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.