Vendor: TeraPixel Technologies, Inc. Category: Video Processing

High Speed Low Power JPEG Codec IP Core

High Speed Low Power JPEG Codec IP Core

Overview

High Speed Low Power JPEG Codec IP Core

Key features

  • ISO/IEC 10918-1/2(JPEG) Compliant
  • Base Line Support (Progressive is not supported)
  • Encode Format
    • Y:CB:CR = 4:2:2, 4:1:1
  • Automatic Header Handling
    • Generate/Read a variety of JPEG header information (Marker Code, Parameter) automatically.
  • Quantization Table
    • Implement 3 quantization tables for Y/Cb/Cr respectively as default.
    • Possible to program tables from external CPU.
  • Encode/Decode process performance
  • 92Mbyte/sec (@100MHz CLK) Same performance for both ENC/DEC
  • (DCT/IDCT, Q/IQ to be processed at 1-pixel/cycle)
  • Example of YUV420
    • 640×480×200fps
    • 1280×1024×70fps

Block Diagram

LDS High Speed JPEG Codec block diagram

What’s Included?

  • Verilog RTL
  • Synthesis Environment
  • Test Environment
  • Datasheet & Documents

Specifications

Identity

Part Number
LDS High Speed JPEG Codec
Vendor
TeraPixel Technologies, Inc.
Type
Silicon IP

Provider

Frequently asked questions about Video Processing IP

What is High Speed Low Power JPEG Codec IP Core?

High Speed Low Power JPEG Codec IP Core is a Video Processing IP core from TeraPixel Technologies, Inc. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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