Vendor: Rambus, Inc. Category: Hash / MAC

SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators

The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2…

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Overview

The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SHA-3 (FIPS-202), supporting the NIST MAC mode up to 6.4 Gbps @ 450MHz. Designed for fast integration, low gate count and full transforms, the HASH-IP-57 accelerators provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.

How the HASH-IP-57 works

The HASH-IP-57 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the HASH-IP-57 is the hash core embedded in the IPsec packet engines as well as VaultIP hardware root of trust cores providing support for MD5 and SHA Hash-based functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2 to 84 Gbps depending on the configuration and area. Gate counts ranges from 14K to 49K gates depending on the configuration.

Key features

  • Wide bus interface (1024-bit data, 512-bit digest) or 32 bit register interface
  • MD5, SHA-1, SHA-2, SHA-3
  • SHA-2/3 in 224/256/384/512 modes
  • Message puffing for all algorithms
  • Message data scheduling hardware
  • Hash context switching and state loading
  • Standard, high frequency and high performance versions available
  • Fully synchronous design

Block Diagram

HASH-IP-57 block diagram

Benefits

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Specifications

Identity

Part Number
HASH-IP-57
Vendor
Rambus, Inc.
Type
Silicon IP

Security

Crypto Algorithm
SHA1 , SHA2 , SHA3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA

Learn more about Hash / MAC IP core

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Frequently asked questions about Hash / MAC IP cores

What is SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators?

SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators is a Hash / MAC IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this Hash / MAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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