Vendor: Rambus, Inc. Category: Hash / MAC

SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators

HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algor…

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Overview

HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2), SHA-2 (FIPS-180-3/4) and SHA-3 (FIPS-202), up to 8 Gbps. Designed for fast integration, low gate count and full transforms, the HMAC-IP-59 accelerators provide a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.

How the HMAC-IP-59 works

The HMAC-IP-59 is a family of the cryptographic library elements in the Rambus hardware IP library (formerly of Inside Secure). For example, the HMAC-IP-59 is the hash core embedded in the IPsec packet engines as well as the VaultIP root of trust cores providing support for MD5 and SHA based Hash and HMAC functions. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.

Sustained performance for any object sizes ranges from 2 to 8 Gbps, depending on the configuration and area. Gate counts ranges from 23K to 95K gates depending on the configuration.

Key features

  • Wide bus interface
  • Supporting HMAC and Basic Hash operations for all algorithms: MD5, SHA-1, SHA-2 (224, 256, 384, 512), SHA-3 (224, 256, 384, 512)
  • MAC Key XOR and Message padding
  • Message data scheduling hardware
  • Calculation of “inner digest” and “outer digest” from a MAC Key input
  • Calculation of “inner hash” and “outer hash” from a MAC Key input or “inner digest” and “outer digest” input
  • MAC Key sizes shorter, equal and longer than algorithm block size
  • Hash and HMAC context switching
  • Continued hash / HMAC support
  • Standard, high frequency and high performance versions available
  • Secure hash standard-compliant FIPS-180-2, FIPS-180-3, FIPS-180-4
  • HMAC support for all algorithms, compliant with FIPS-198-1, FIPS-198
  • Fully synchronous design

Block Diagram

HMAC-IP-59 block diagram

Benefits

  • Silicon-proven implementation
  • Fast and easy to integrate into SoCs
  • Flexible layered design
  • Complete range of configurations
  • World-class technical support

Specifications

Identity

Part Number
HMAC-IP-59
Vendor
Rambus, Inc.
Type
Silicon IP

Security

Crypto Algorithm
SHA1 , SHA2 , SHA3

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA

Learn more about Hash / MAC IP core

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Frequently asked questions about Hash / MAC IP cores

What is SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators?

SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators is a Hash / MAC IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this Hash / MAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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