AVC (H.264) CABAC Encoder IP Core
The CABAC Encoder IP Core is designed for context-adaptive binary arithmetic coding.
- H.264 / AVC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
AVC (H.264) CABAC Encoder IP Core
The CABAC Encoder IP Core is designed for context-adaptive binary arithmetic coding.
Video Output Port IP Core is a compact and high-performance functional block for embedded system that collects and outputs graphi…
SATA Controller IP Core is ideal for use in a variety of storage application which require high speed data transfer, cost, scalab…
CSI-2 receiver controller for application processor
Mature controller solution for OTG and Device applications
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi…
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latc…
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an cell design ena…
10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
Brite provides USB2.0 OTG PHY which is a mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (So…
RF I/O Pad Set and Discrete RF ESD Protection Components
The RF library include analog signal pads and ESD protection components for RF applications.
Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a flexible and c…
95 dB of SNR, 24-bit audio CODEC with headphone output and line-out
SoC integrators targeting portable audio applications such as Smart Phones, PMP, PDA should demonstrate optimal recording perform…
RTP/UDP/IP Protocol Hardware Stack – Raw, Uncompressed RGB/YUV Video Streams Packet Processing
The DB-RTP-UDP-IP Intellectual Property Core is an RTP/UDP/IP Protocol Hardware Stack with the following protocol processing unit…
I2C Controller IP – Slave, User Register Interface, No CPU Required
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal conf…
Half Precision IEEE-754R complete FPU for graphics processing
The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for…
Asynchronous FIFO with configurable flags and counts
The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
Synchronous FIFO with configurable flags and counts
The sFIFO controls are designed to operate over a wide range of clock frequencies.